A Fully Pipelined FIFO Based Polynomial Multiplication Hardware
Architecture Based On Number Theoretic Transform
A Fully Pipelined FIFO Based Polynomial Multiplication Hardware
Architecture Based On Number Theoretic Transform
This paper presents digital hardware for computing polynomial multiplication using Number Theoretic Transform (NTT), specifically designed for implementation on Field Programmable Gate Arrays (FPGAs). Multiplying two large polynomials applies to many modern encryption schemes, including those based on Ring Learning with Error (RLWE). The proposed design uses First In, First …