A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug
A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug
Reconstructing system-level behavior from silicon traces is a critical problem in post-silicon validation of System-on-Chip designs. Current industrial practice in this area is primarily manual, depending on collaborative insights of the architects, designers, and validators. This paper presents a trace analysis approach that exploits architectural models of system-level protocols to …