Hybrid Cell Assignment and Sizing for Power, Area, Delay-Product Optimization of SRAM Arrays
Hybrid Cell Assignment and Sizing for Power, Area, Delay-Product Optimization of SRAM Arrays
Memory accounts for a considerable portion of the total power budget and area of digital systems. Furthermore, it is typically the performance bottleneck of the processing units. Therefore, it is critical to optimize the memory with respect to the product of power, area, and delay (PAD). We propose a hybrid …