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Developments toward a 250-nm, Fully Planarized Fabrication Process with Ten Superconducting Layers and Self-Shunted Josephson Junctions

Developments toward a 250-nm, Fully Planarized Fabrication Process with Ten Superconducting Layers and Self-Shunted Josephson Junctions

We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance …