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Subthreshold channels at the edges of nanoscale triple-gate silicon transistors
The authors investigate the subthreshold behavior of triple-gate silicon field-effect transistors by low-temperature transport experiments. These three-dimensional nanoscale devices consist of a lithographically defined silicon nanowire surrounded by a gate with an active region as small as a few tens of nanometers down to 50×60×35nm3. Conductance versus gate voltage shows …