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Engineering Nanowire n-MOSFETs at <formula formulatype="inline"><tex Notation="TeX">$L_{g}<8~{\rm nm}$</tex></formula>

Engineering Nanowire n-MOSFETs at <formula formulatype="inline"><tex Notation="TeX">$L_{g}<8~{\rm nm}$</tex></formula>

As metal-oxide-semiconductor field-effect transistors (MOSFET) channel lengths (Lg) are scaled to lengths shorter than Lg<8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown …