Demonstration of two-dimensional connectivity for a scalable error-corrected ion-trap quantum processor architecture

Marco Valentini, Martin W. van Mourik, Friederike Butt, Jakob Wahl, Matthias Dietl, Michael Pfeifer, Fabian Anmasser, Yves Colombe, Clemens Rössler, Philip C. Holz

Abstract

A major hurdle for building a large-scale quantum computer is to scale up the number of qubits while maintaining connectivity between them. In trapped-ion devices, this connectivity can be provided by physically moving subregisters consisting of a few ions across the processor. The topology of the connectivity is given by the layout of the ion trap where one-dimensional and two-dimensional arrangements are possible. Here, we focus on an architecture based on a rectangular two-dimensional lattice, where each lattice site contains a subregister with a linear string of ions. We refer to this architecture as the Quantum Spring Array (QSA). Subregisters placed in neighboring lattice sites can be coupled by bringing the respective ion strings close to each other while avoiding merging them into a single trapping potential. Control of the separation of subregisters along one axis of the lattice, known as the axial direction, uses quasi-static voltages, while the second axis, the radial, requires control of radio frequency signals. In this work, we investigate key elements of the 2D lattice quantum computation architecture along both axes: We show that the coupling rate between neighboring lattice sites increases with the number of ions per site and the motion of the coupled system can be resilient to noise. The coherence of the coupling is assessed, and an entangled state of qubits in separate trapping regions along the radial axis is demonstrated. Moreover, we demonstrate control over radio frequency signals to adjust radial separation between strings, and thus tune their coupling rate. We further map the 2D lattice architecture to code primitives for fault-tolerant quantum error correction, providing a step towards a quantum processor architecture that is optimized for large-scale fault-tolerant operation.

Locations

• arXiv (Cornell University) - View - PDF