Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic

Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth M. O'Brien, Yaman Umuroglu, Miriam Leeser

Type: Preprint

Publication Date: 2018-06-26

Citations: 1

View Publication

Locations

arXiv (Cornell University) - View

Similar Works

Action	Title	Year	Authors
+	Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic	2018	Michaela Blott Thomas B. Preußer Nicholas C. Fraser Giulio Gambardella Kenneth M. O'Brien Yaman Umuroglu Miriam Leeser
+ PDF Chat	Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic	2017	Michaela Blott Thomas B. Preuber Nicholas J. Fraser Giulio Gambardella Kenneth M. O'Brien Yaman Umuroglu Miriam Leeser
+	Scaling Binarized Neural Networks on Reconfigurable Logic	2017	Nicholas J. Fraser Yaman Umuroglu Giulio Gambardella Michaela Blott Philip H. W. Leong Magnus Jahre Kees Vissers
+ PDF Chat	Scaling Binarized Neural Networks on Reconfigurable Logic	2017	Nicholas J. Fraser Yaman Umuroglu Giulio Gambardella Michaela Blott Philip H. W. Leong Magnus Jahre Kees Vissers
+	Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs	2018	Philip Colangelo Nasibeh Nasiri Asit K. Mishra Eriko Nurvitadhi Martin Margala Kevin Nealis
+	Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks	2017	Hokchhay Tann Soheil Hashemi R. Iris Bahar Sherief Reda
+	Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks	2017	Hokchhay Tann Soheil Hashemi Iris Bahar Sherief Reda
+ PDF Chat	Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks	2017	Hokchhay Tann Soheil Hashemi R. Iris Bahar Sherief Reda
+ PDF Chat	AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers	2019	Julian Faraone Martin Kumm Martin Hardieck Peter Zipf Xueyuan Liu David Boland Philip H. W. Leong
+	Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation	2023	Stylianos I. Venieris Javier Fernández-Marqués Nicholas D. Lane
+ PDF Chat	Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration	2022	R. Elangovan Shubham Jain Anand Raghunathan
+	Ax-BxP: Approximate Blocked Computation for Precision-Reconfigurable Deep Neural Network Acceleration	2020	R. Elangovan Shubham Jain Anand Raghunathan
+	Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic	2018	Su Jiang Nicholas J. Fraser Giulio Gambardella Michaela Blott Gianluca Durelli David B. Thomas Philip H. W. Leong Peter Y. K. Cheung
+ PDF Chat	LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference	2020	Erwei Wang James J. Davis Peter Y. K. Cheung George A. Constantinides
+	Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation	2023	Stylianos I. Venieris Javier Fernández-Marqués Nicholas D. Lane
+	FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations	2020	Yichi Zhang Junhao Pan Xinheng Liu Hongzheng Chen Deming Chen Zhiru Zhang
+ PDF Chat	FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations	2020	Yichi Zhang Junhao Pan Xinheng Liu Hongzheng Chen Deming Chen Zhiru Zhang
+	FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations	2020	Yichi Zhang Junhao Pan Xinheng Liu Hongzheng Chen Deming Chen Zhiru Zhang
+ PDF Chat	Streaming Architecture for Large-Scale Quantized Neural Networks on an FPGA-Based Dataflow Platform	2018	Chaim Baskin Natan Liss Evgenii Zheltonozhskii Alex Bronstein Avi Mendelson
+ PDF Chat	LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network Inference	2024	Yanyue Xie Zhengang Li Dana Diaconu Suranga Handagala Miriam Leeser Xue Lin

Works That Cite This (0)

Action	Title	Year	Authors

Works Cited by This (5)

Action	Title	Year	Authors
+	Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1	2016	Matthieu Courbariaux Itay Hubara Daniel Soudry Ran El‐Yaniv Yoshua Bengio
+	DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients	2016	Shuchang Zhou Yuxin Wu Zekun Ni Xinyu Zhou He Wen Yuheng Zou
+	Deep Learning with Low Precision by Half-wave Gaussian Quantization	2017	Zhaowei Cai Xiaodong He Jian Sun Nuno Vasconcelos
+ PDF Chat	Generic and universal parallel matrix summation with a flexible compression goal for Xilinx FPGAs	2017	Thomas B. Preuser
+ PDF Chat	FINN	2017	Yaman Umuroglu Nicholas J. Fraser Giulio Gambardella Michaela Blott Philip H. W. Leong Magnus Jahre Kees Vissers