Engineering › Electrical and Electronic Engineering

Radiation Effects in Electronics

Works Count: 35287

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Description

This cluster of papers focuses on the challenges and techniques for fault tolerance in electronic systems, particularly in the context of soft errors, radiation effects, and single event upsets in CMOS technology. It explores various methods for error detection, reliability evaluation, and mitigation of transient faults in nanoelectronics.

Keywords

Soft Errors; Radiation Effects; Error Detection; Fault Tolerance; CMOS Technology; Single Event Upsets; Reliability Evaluation; Nanoelectronics; Transient Faults; Dependability

Design & analysis of fault tolerant digital systems

1988-10-01

B.W. Johnson

Handbook of radiation effects

1994-06-01

Andrew Holmes‐Siedle , Len Adams

Introduction. 1: Radiation environments. 2: The response of materials and devices to radiation. 3: Metal-oxide semiconductor (MOS) devices. 4: Discrete bipolar transistors. 5: Diodes, solar cells, and opto-electronics. 6: Power … Introduction. 1: Radiation environments. 2: The response of materials and devices to radiation. 3: Metal-oxide semiconductor (MOS) devices. 4: Discrete bipolar transistors. 5: Diodes, solar cells, and opto-electronics. 6: Power devices. 7: Optical media. 8: Other components. 9: Polymers and other organics. 10: The interaction of space radiation with shielding materials. 11: Computer methods for particle transport. 12: Radiation testing. 13: Radiation-hardening of parts. 14: Equipment hardening and hardness assurance. 15: Conclusions. Appendices. A. Useful general and geophysical data. B. Useful radiation data. C. Useful data on materials. D. Radiation response data for electronic components. E. Depth-dose curves for representative satellite orbits. F. Degradation in polymers. Index

The Effects of Radiation on Electronic Systems

1986-01-01

George C. Messenger , Milton S. Ash

IBM experiments in soft fails in computer electronics (1978–1994)

1996-01-01

J. F. Ziegler , H. W. Curtis , H. P. Muhlfeld +7 more

This historical review covers IBM experiments in evaluating radiation-induced soft fails in LSI electronics over a fifteen-year period, concentrating on major scientific and technical advances which have not been previously … This historical review covers IBM experiments in evaluating radiation-induced soft fails in LSI electronics over a fifteen-year period, concentrating on major scientific and technical advances which have not been previously published.

Concurrent error detection using watchdog processors-a survey

1988-01-01

Asif Mahmood , E.J. McCluskey

Concurrent system-level error detection techniques using a watchdog processor are surveyed. A watchdog processor is a small and simple coprocessor that detects errors by monitoring the behavior of a system. … Concurrent system-level error detection techniques using a watchdog processor are surveyed. A watchdog processor is a small and simple coprocessor that detects errors by monitoring the behavior of a system. Like replication, it does not depend on any fault model for error detection. However, it requires less hardware than replication. It is shown that a large number of errors can be detected by monitoring the control flow and memory-access behavior. Two techniques for control-flow checking are discussed and compared with current error-detection techniques. A scheme for memory-access checking based on capability-based addressing is described. The design of a watchdog for performing reasonable checks on the output of a main processor by executing assertions is discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>

Accurate condensed history Monte Carlo simulation of electron transport. I. <scp>EGS</scp>nrc, the new <scp>EGS4</scp> version

2000-03-01

I. Kawrakow

In this report a new EGS4 version, called EGS nrc to reflect the substantial changes made to the original code is reported, which incorporates a new any‐angle multiple elastic scattering … In this report a new EGS4 version, called EGS nrc to reflect the substantial changes made to the original code is reported, which incorporates a new any‐angle multiple elastic scattering theory, an improved electron‐step algorithm, a correct implementation of the fictitious cross section method for sampling distances between discrete interactions, a more accurate evaluation of energy loss, as well as an exact boundary crossing algorithm. It is demonstrated that EGS nrc allows for an artifact free Monte Carlo simulation of ion chamber response and backscattering, situations that have been considered in the past as the two of the most stringent tests of condensed history Monte Carlo codes. A detailed discussion of the effect of the various components of the condensed history simulation of electron transport on the simulated ion chamber response is given in the accompanying paper.

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Range and stopping-power tables for heavy ions

1970-01-01

L. C. Northcliffe , Roland Schilling

Application of Boolean algebra to switching circuit design and to error detection

1954-09-01

David E. Muller

A solution is sought to the general problem of simplifying switching circuits that have more than one output. The mathematical treatment of the problem applies only to circuits that may … A solution is sought to the general problem of simplifying switching circuits that have more than one output. The mathematical treatment of the problem applies only to circuits that may be represented by "polynomials" in Boolean algebra. It is shown that certain parts of the multiple output problem for such circuits may be reduced to a single output problem whose inputs are equal in number to the sum of the numbers of inputs and outputs in the original problem. A particularly simple reduction may be effected in the case of two outputs. Various techniques are described for simplifying Boolean expressions, called "+ polynomials," in which the operation "exclusive or" appears between terms. The methods described are particularly suitable for use with an automatic computer, and have been tested on the Illiac. An unexpected metric relationship is shown to exist between the members of certain classes of "+ polynomials" called "nets." This relationship may be used for constructing error-detecting codes, provided the number of bits in the code is a power of two.

A Class of Optimal Minimum Odd-weight-column SEC-DED Codes

1970-07-01

M. Y. Hsiao

The class of codes described in this paper is used for single-error correction and double-error detection (SEC-DED). It is equivalent to the Hamming SEC-DED code in the sense that for … The class of codes described in this paper is used for single-error correction and double-error detection (SEC-DED). It is equivalent to the Hamming SEC-DED code in the sense that for a specified number k of data bits, the same number of check bits r is used. The minimum odd-weight-column code is suitable for applications to computer memories or parallel systems. A computation indicates that this code is better in performance, cost and reliability than are conventional Hamming SEC-DED codes.

Alpha-particle-induced soft errors in dynamic memories

1979-01-01

T.C. May , M. H. Woods

A new physical soft error mechanism in dynamic RAM's and CCD's is the upset of stored data by the passage of alpha particles through the memory array area. The alpha … A new physical soft error mechanism in dynamic RAM's and CCD's is the upset of stored data by the passage of alpha particles through the memory array area. The alpha particles are emitted by the radioactive decay of uranium and thorium which are present in parts-per-million levels in packaging materials. When an alpha particle penetrates the die surface, it can create enough electron-hole pairs near a storage node to cause a random, single-bit error. Results of experiments and measurements of alpha activity of materials are reported and a physical model for the soft error is developed. Implications for the future of dynamic memories are also discussed.

Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review

1984-03-01

C. L. Chen , M. Y. Hsiao

This paper presents a state-of-the-art review of error-correcting codes for computer semiconductor memory applications. The construction of four classes of error-correcting codes appropriate for semiconductor memory designs is described, and … This paper presents a state-of-the-art review of error-correcting codes for computer semiconductor memory applications. The construction of four classes of error-correcting codes appropriate for semiconductor memory designs is described, and for each class of codes the number of check bits required for commonly used data lengths is provided. The implementation aspects of error correction and error detection are also discussed, and certain algorithms useful in extending the error-correcting capability for the correction of soft errors such as α-particle-induced errors are examined in some detail.

Terrestrial cosmic rays

1996-01-01

J. F. Ziegler

This paper reviews the basic physics of those cosmic rays which can affect terrestrial electronics. Cosmic rays at sea level consist mostly of neutrons, protons, pions, muons, electrons, and photons. … This paper reviews the basic physics of those cosmic rays which can affect terrestrial electronics. Cosmic rays at sea level consist mostly of neutrons, protons, pions, muons, electrons, and photons. The particles which cause significant soft fails in electronics are those particles with the strong interaction: neutrons, protons, and pions. At sea level, about 95% of these particles are neutrons. The quantitative flux of neutrons can be estimated to within 3×, and the relative variation in neutron flux with latitude, altitude, diurnal time, earth's sidereal position, and solar cycle is known with even higher accuracy. The possibility of two particles of a cascade interacting with a single circuit to cause two simultaneous errors is discussed. The terrestrial flux of nucleons can be attenuated by shielding, making a significant reduction in the electronic system soft-error rate. Estimates of such attenuation are made.

SWIFT: Software Implemented Fault Tolerance

2005-03-31

George A. Reis , Jonathan Chang , Neil Vachharajani +2 more

To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. However, these advances make processors more … To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. However, these advances make processors more susceptible to transient faults that can affect correctness. While reliable systems typically employ hardware techniques to address soft-errors, software techniques can provide a lower-cost and more flexible alternative. This paper presents a novel, software-only, transient-fault-detection technique, called SWIFT. SWIFT efficiently manages redundancy by reclaiming unused instruction-level resources present during the execution of most programs. SWIFT also provides a high level of protection and performance with an enhanced control-flow checking mechanism. We evaluate an implementation of SWIFT on an Itanium 2 which demonstrates exceptional fault coverage with a reasonable performance cost. Compared to the best known single-threaded approach utilizing an ECC memory system, SWIFT demonstrates a 51% average speedup.

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Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits

1978-05-06

Ronald L. Wadsack

This paper addresses the simulation and detection of logic faults in CMOS integrated circuits. CMOS logic gates are intrinsically tri-state devices: output low, output high, or output open. This third, … This paper addresses the simulation and detection of logic faults in CMOS integrated circuits. CMOS logic gates are intrinsically tri-state devices: output low, output high, or output open. This third, high-impedance condition introduces a new, nonclassical logic fault: the “stuck-open.” The paper describes the modeling of this fault and its complement, the stuck-on, by means of gate-level networks. In addition, this paper provides a methodology for creating simulator models for tri-state and other dynamic circuit elements. The models are gate-level in structure, provide for both classical and stuck-open/stuck-on faults, and can be adopted for use on essentially any general purpose logic simulator.

Upset hardened memory design for submicron CMOS technology

1996-12-01

T. Calin , M. Nicolaidis , Raoul Velazco

A novel design technique is proposed for storage elements which are insensitive to radiation-induced single-event upsets. This technique is suitable for implementation in high density ASICs and static RAMs using … A novel design technique is proposed for storage elements which are insensitive to radiation-induced single-event upsets. This technique is suitable for implementation in high density ASICs and static RAMs using submicron CMOS technology.

Total-Ionizing-Dose Effects in Modern CMOS Technologies

2006-12-01

Hugh J. Barnaby

This review paper discusses several key issues associated with deep submicron CMOS devices as well as advanced semiconductor materials in ionizing radiation environments. There are, as outlined in the ITRS … This review paper discusses several key issues associated with deep submicron CMOS devices as well as advanced semiconductor materials in ionizing radiation environments. There are, as outlined in the ITRS roadmap, numerous challenges ahead for commercial industry in its effort to track Moore's Law down to the 45 nm node and beyond. While many of the classical threats posed by ionizing radiation exposure have diminished by aggressive semiconductor scaling, the question remains whether there may be unknown, potentially worse threats lurking in the deep submicron regime. This manuscript provides a basic overview of some of the materials, devices, and designs that are being explored or, in some cases, used today. An overview of radiation threats and how radiation effects can be characterized is also presented. Last, the paper provides a detailed discussion of what we know now about how modern devices and materials respond to radiation and how we may assess, through the use of advanced analysis and modeling techniques, the relative hardness of future technologies

Error-Correcting Codes.

1962-01-01

R. G. Gallager , W. W. Peterson

Characterization of soft errors caused by single event upsets in CMOS processes

2004-04-01

Tanay Karnik , P. Hazucha

Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade … Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

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Detailed design and evaluation of redundant multithreading alternatives

2002-05-01

Shubhendu S. Mukherjee , Michael J. Kontz , Steven K. Reinhardt

Exponential growth in the number of on-chip transistors, coupled with reductions in voltage levels, makes each generation of microprocessors increasingly vulnerable to transient faults. In a multithreaded environment, we can … Exponential growth in the number of on-chip transistors, coupled with reductions in voltage levels, makes each generation of microprocessors increasingly vulnerable to transient faults. In a multithreaded environment, we can detect these faults by running two copies of the same program as separate threads, feeding them identical inputs, and comparing their outputs, a technique we call Redundant Multithreading (RMT).This paper studies RMT techniques in the context of both single- and dual-processor simultaneous multithreaded (SMT) single-chip devices. Using a detailed, commercial-grade, SMT processor design we uncover subtle RMT implementation complexities, and find that RMT can be a more significant burden for single-processor devices than prior studies indicate. However, a novel application of RMT techniques in a dual-processor device, which we term chip-level redundant threading (CRT), shows higher performance than lockstepping the two cores, especially on multithreaded workloads.

Single event upset at ground level

1996-12-01

E. Normand

Ground level upsets have been observed in computer systems containing large amounts of random access memory (RAM). Atmospheric neutrons are most likely the major cause of the upsets based on … Ground level upsets have been observed in computer systems containing large amounts of random access memory (RAM). Atmospheric neutrons are most likely the major cause of the upsets based on measured data using the Weapons Neutron Research (WNR) neutron beam.

Radiation effects in SOI technologies

2003-06-01

J.R. Schwank , V. Ferlet-Cavrois , M.R. Shaneyfelt +2 more

Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose … Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.

Fault injection for dependability validation: a methodology and some applications

1990-01-01

Jean Arlat , M. Ángeles López Aguera , L. Amat +5 more

The authors address the problem of validating the dependability of fault-tolerant computing systems, in particular, the validation of the fault-tolerance mechanisms. The proposed approach is based on the use of … The authors address the problem of validating the dependability of fault-tolerant computing systems, in particular, the validation of the fault-tolerance mechanisms. The proposed approach is based on the use of fault injection at the physical level on a hardware/software prototype of the system considered. The place of this approach in a validation-directed design process and with respect to related work on fault injection is clearly identified. The major requirements and problems related to the development and application of a validation methodology based on fault injection are presented and discussed. Emphasis is put on the definition, analysis, and use of the experimental dependability measures that can be obtained. The proposed methodology has been implemented through the realization of a general pin-level fault injection tool (MESSALINE), and its usefulness is demonstrated by the application of MESSALINE to the experimental validation of two systems: a subsystem of a centralized computerized interlocking system for railway control applications and a distributed system corresponding to the current implementation of the dependable communication system of the ESPRIT Delta-4 Project.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>

Error detection by duplicated instructions in super-scalar processors

2002-03-01

Nahmsuk Oh , P.P. Shirvani , E.J. McCluskey

This paper proposes a pure software technique "error detection by duplicated instructions" (EDDI), for detecting errors during usual system operation. Compared to other error-detection techniques that use hardware redundancy, EDDI … This paper proposes a pure software technique "error detection by duplicated instructions" (EDDI), for detecting errors during usual system operation. Compared to other error-detection techniques that use hardware redundancy, EDDI does not require any hardware modifications to add error detection capability to the original system. EDDI duplicates instructions during compilation and uses different registers and variables for the new instructions. Especially for the fault in the code segment of memory, formulas are derived to estimate the error-detection coverage of EDDI using probabilistic methods. These formulas use statistics of the program, which are collected during compilation. EDDI was applied to eight benchmark programs and the error-detection coverage was estimated. Then, the estimates were verified by simulation, in which a fault injector forced a bit-flip in the code segment of executable machine codes. The simulation results validated the estimated fault coverage and show that approximately 1.5% of injected faults produced incorrect results in eight benchmark programs with EDDI, while on average, 20% of injected faults produced undetected incorrect results in the programs without EDDI. Based on the theoretical estimates and actual fault-injection experiments, EDDI can provide over 98% fault-coverage without any extra hardware for error detection. This pure software technique is especially useful when designers cannot change the hardware, but they need dependability in the computer system. To reduce the performance overhead, EDDI schedules the instructions that are added for detecting errors such that "instruction-level parallelism" (ILP) is maximized. Performance overhead can be reduced by increasing ILP within a single super-scalar processor. The execution time overhead in a 4-way super-scalar processor is less than the execution time overhead in the processors that can issue two instructions in one cycle.

Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule

2010-05-27

Eishi Ibe , Hitoshi Taniguchi , Y. Yahagi +2 more

Trends in terrestrial neutron-induced soft-error in SRAMs from a 250 nm to a 22 nm process are reviewed and predicted using the Monte-Carlo simulator CORIMS, which is validated to have … Trends in terrestrial neutron-induced soft-error in SRAMs from a 250 nm to a 22 nm process are reviewed and predicted using the Monte-Carlo simulator CORIMS, which is validated to have less than 20% variations from experimental soft-error data on 180-130 nm SRAMs in a wide variety of neutron fields like field tests at low and high altitudes and accelerator tests in LANSCE, TSL, and CYRIC. The following results are obtained: 1) Soft-error rates per device in SRAMs will increase x6-7 from 130 nm to 22 nm process; 2) As SRAM is scaled down to a smaller size, soft-error rate is dominated more significantly by low-energy neutrons (<; 10 MeV); and 3) The area affected by one nuclear reaction spreads over 1 M bits and bit multiplicity of multi-cell upset become as high as 100 bits and more.

Basic mechanisms and modeling of single-event upset in digital microelectronics

2003-06-01

P.E. Dodd , L. W. Massengill

Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and … Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

Impact of CMOS technology scaling on the atmospheric neutron soft error rate

2000-12-01

P. Hazucha , C. Svensson

We investigated scaling of the atmospheric neutron soft error rate (SER) which affects reliability of CMOS circuits at ground level and airplane flight altitudes. We considered CMOS circuits manufactured in … We investigated scaling of the atmospheric neutron soft error rate (SER) which affects reliability of CMOS circuits at ground level and airplane flight altitudes. We considered CMOS circuits manufactured in a bulk process with a lightly-doped p-type wafer. One method, based on the empirical model, predicts a linear decrease of SER per bit with decreasing feature size L/sub G/. A different method, based on the MBGR model, predicts even faster decrease of SER per bit than linear. If the increasing number of bits is taken into account, then the SER per chip is not expected to increase faster than linearly with decreasing L/sub G/.

Fault injection techniques and tools

1997-04-01

Mei-Chen Hsueh , Timothy Tsai , Ravishankar K. Iyer

Fault injection is important to evaluating the dependability of computer systems. Researchers and engineers have created many novel methods to inject faults, which can be implemented in both hardware and … Fault injection is important to evaluating the dependability of computer systems. Researchers and engineers have created many novel methods to inject faults, which can be implemented in both hardware and software. The contrast between the hardware and software methods lies mainly in the fault injection points they can access, the cost and the level of perturbation. Hardware methods can inject faults into chip pins and internal components, such as combinational circuits and registers that are not software-addressable. On the other hand, software methods are convenient for directly producing changes at the software-state level. Thus, we use hardware methods to evaluate low-level error detection and masking mechanisms, and software methods to test higher level mechanisms. Software methods are less expensive, but they also incur a higher perturbation overhead because they execute software on the target system.

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DIVA: a reliable substrate for deep submicron microarchitecture design

1999-11-16

Todd Austin

Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that work reliably in varied (and occasionally adverse) operating conditions. … Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that work reliably in varied (and occasionally adverse) operating conditions. To further complicate this task, deep submicron fabrication technologies present new reliability challenges in the form of degraded signal quality and logic failures caused by natural radiation interference. In this paper, we introduce dynamic verification, a novel microarchitectural technique that can significantly reduce the burden of correctness in microprocessor designs. The approach works by augmenting the commit phase of the processor pipeline with a functional checker unit. The functional checker verifies the correctness of the core processor's computation, only permitting correct results to commit. Overall design cost can be dramatically reduced because designers need only verify the correctness of the checker unit. We detail the DIVA checker architecture, a design optimized for simplicity and low cost. Using detailed timing simulation, we show that even resource-frugal DIVA checkers have little impact on core processor performance. To make the case for reduced verification costs, we argue that the DIVA checker should lend itself to functional and electrical verification better than a complex core processor. Finally, future applications that leverage dynamic verification to increase processor performance and availability are suggested.

Soft Errors in Advanced Computer Systems

2005-05-01

R. Baumann

As the dimensions and operating voltages of computer electronics shrink to satisfy consumers' insatiable demand for higher density, greater functionality, and lower power consumption, sensitivity to radiation increases dramatically. In … As the dimensions and operating voltages of computer electronics shrink to satisfy consumers' insatiable demand for higher density, greater functionality, and lower power consumption, sensitivity to radiation increases dramatically. In terrestrial applications, the predominant radiation issue is the soft error, whereby a single radiation event causes a data bit stored in a device to be corrupted until new data is written to that device. This article comprehensively analyzes soft-error sensitivity in modern systems and shows it to be application dependent. The discussion covers ground-level radiation mechanisms that have the most serious impact on circuit operation along with the effect of technology scaling on soft-error rates in memory and logic.

Dynamic fault-tree models for fault-tolerant computer systems

1992-01-01

J.B. Dugan , Salvatore J. Bavuso , Mark Boyd

Reliability analysis of fault-tolerant computer systems for critical applications is complicated by several factors. Systems designed to achieve high levels of reliability frequently employ high levels of redundancy, dynamic redundancy … Reliability analysis of fault-tolerant computer systems for critical applications is complicated by several factors. Systems designed to achieve high levels of reliability frequently employ high levels of redundancy, dynamic redundancy management, and complex fault and error recovery techniques. This paper describes dynamic fault-tree modeling techniques for handling these difficulties. Three advanced fault-tolerant computer systems are described: a fault-tolerant parallel processor, a mission avionics system, and a fault-tolerant hypercube. Fault-tree models for their analysis are presented. HARP (Hybrid Automated Reliability Predictor) is a software package developed at Duke University and NASA Langley Research Center that can solve those fault-tree models.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>

Robust system design with built-in soft-error resilience

2005-02-01

Subhasish Mitra , N. Seifert , M. Zhang +2 more

Transient errors caused by terrestrial radiation pose a major barrier to robust system design. A system's susceptibility to such errors increases in advanced technologies, making the incorporation of effective protection … Transient errors caused by terrestrial radiation pose a major barrier to robust system design. A system's susceptibility to such errors increases in advanced technologies, making the incorporation of effective protection mechanisms into chip designs essential. A new design paradigm reuses design-for-testability and debug resources to eliminate such errors.

Modeling the effect of technology trends on the soft error rate of combinational logic

2003-06-25

Premkishore Shivakumar , Michael Kistler , Stephen W. Keckler +2 more

This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model … This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latching-window masking, which inhibit soft errors in combinational logic. We quantify the SER due to high-energy neutrons in SRAM cells, latches, and logic circuits for feature sizes from 600 nm to 50 nm and clock periods from 16 to 6 fan-out-of-4 inverter delays. Our model predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes that computer system designers must address the risks of soft errors in logic circuits for future designs.

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Control-flow checking by software signatures

2002-03-01

Nahmsuk Oh , P.P. Shirvani , E.J. McCluskey

This paper presents a new signature monitoring technique, CFCSS (control flow checking by software signatures); CFCSS is a pure software method that checks the control flow of a program using … This paper presents a new signature monitoring technique, CFCSS (control flow checking by software signatures); CFCSS is a pure software method that checks the control flow of a program using assigned signatures. An algorithm assigns a unique signature to each node in the program graph and adds instructions for error detection. Signatures are embedded in the program during compilation time using the constant field of the instructions and compared with run-time signatures when the program is executed. Another algorithm reduces the code size and execution time overhead caused by checking instructions in CFCSS. A "branching fault injection experiment" was performed with benchmark programs. Without CFCSS, an average of 33.7 % of the injected branching faults produced undetected incorrect outputs; however, with CFCSS, only 3.1 % of branching faults produced undetected incorrect outputs. Thus it is possible to increase error detection coverage for control flow errors by an order of magnitude using CFCSS. The distinctive advantage of CFCSS over previous signature monitoring techniques is that CFCSS is a pure software method, i.e., it needs no dedicated hardware such as a watchdog processor for control flow checking. A watchdog task in multitasking environment also needs no extra hardware, but the advantage of CFCSS over a watchdog task is that CFCSS can be used even when the operating system does not support multitasking.

Error Detecting and Error Correcting Codes (1950)

2021-02-02

R. W. Hamming

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Radiation-Induced Soft Errors in Advanced Semiconductor Technologies

2005-01-01

Robert Baumann

The once-ephemeral radiation-induced soft error has become a key threat to advanced commercial electronic components and systems. Left unchallenged, soft errors have the potential for inducing the highest failure rate … The once-ephemeral radiation-induced soft error has become a key threat to advanced commercial electronic components and systems. Left unchallenged, soft errors have the potential for inducing the highest failure rate of all other reliability mechanisms combined. This article briefly reviews the types of failure modes for soft errors, the three dominant radiation mechanisms responsible for creating soft errors in terrestrial applications, and how these soft errors are generated by the collection of radiation-induced charge. The soft error sensitivity as a function of technology scaling for various memory and logic components is then presented with a consideration of which applications are most likely to require soft error mitigation.

Error Correcting Codes

1961-11-01

Hendrik Mann , W. W. Peterson

A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor

2004-05-06

S. Mukherjee , Christopher Weaver , Joel Emer +2 more

Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transients faults exist, but come at a cost. Designers clearly require accurate … Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transients faults exist, but come at a cost. Designers clearly require accurate estimates of processor error rates to make appropriate cost/reliability tradeoffs. This paper describes a method for generating these estimates. A key aspect of this analysis is that some single-bit faults (such as those occurring in the branch predictor) do not produce an error in a program's output. We define a structure's architectural vulnerability factor (AVF) as the probability that a fault in that particular structure do not result in an error. A structure's error rate is the product of its raw error rate, as determined by process and circuit technology, and the AVF. Unfortunately, computing AVFs of complex structures, such as the instruction queue, can be quite involved. We identify numerous cases, such as prefetches, dynamically dead code, and wrong-path instructions, in which a fault do not affect, correct execution. We instrument a detailed 1A64 processor simulator to map bit-level microarchitectural state to these cases, generating per-structure AVF estimates. This analysis shows AVFs of 28% and 9% for the instruction queue and execution units, respectively, averaged across dynamic sections of the entire CPU2000 benchmark suite.

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Radiation Effects in Advanced Semiconductor Materials and Devices

2002-01-01

Cor Claeys , Eddy Simoen

The Influence of Protons on the Physical Processes in Bipolar Transistors

2025-06-23

V. Kotlyarov , В. Анциферова | Modeling of systems and processes

Semiconductor devices operating in radiation environ-ments are subject to significant parameter degradation due to the impact of high-energy protons. In this work, a detailed analysis is presented on the influence … Semiconductor devices operating in radiation environ-ments are subject to significant parameter degradation due to the impact of high-energy protons. In this work, a detailed analysis is presented on the influence of proton irradiation on the physical processes in bipolar transistors (BT) used in analog and high-frequency circuits. The study examines the primary damage mechanisms, including ionization effects (charge accumulation in dielectric layers and formation of interface defects) and displacement effects (formation of vacancies and interstitial defects) that lead to the emergence of recombination centers. The investigation of changes in the electrical characteristics of BT is carried out using accelerator experiments, where samples are irra-diated with a proton beam. Modern modeling methods, such as TCAD simulations and analytical models, are em-ployed to establish the relationship between parameter changes and the proton fluence. The experimental results demonstrate that even at moderate doses, there is a significant reduction in current gain and an increase in leakage currents, which adversely affect circuit performance. The paper discusses approaches to enhancing the radiation hardness of BT through the optimization of technological processes, the use of silicongermanium heterojunction transistors (SiGe HBT), and the application of silicon-on-insulator (SOI) technology. The recommendations provid-ed can be applied to the development of radiation-hardened electronic devices intended for use in space elec-tronics. The obtained recommendations can be used for the development of radiation-resistant electronic devices in-tended for operation in space electronics, where protons with energies > 100 MeV additionally cause single radia-tion events (SEE).

Architecture of a test structure for verification of libraries of standard elements in silicon based on a pipeline-distribution approach

2025-06-23

Sergey Il'in , S. V. Gavrilov | Modeling of systems and processes

The paper proposes an architecture of a test structure for verifying libraries of standard cells in silicon, based on a pipeline-distributive approach. This approach allows reducing both the number of … The paper proposes an architecture of a test structure for verifying libraries of standard cells in silicon, based on a pipeline-distributive approach. This approach allows reducing both the number of inputs and outputs and the area occupied by the test structure on a crystal in comparison with traditional approaches. The components of the test structure and the relationships between them are listed. The main attention is paid to the use of multiplexers and demultiplexers for controlling the processes of selection, control and output of signals. Several options for arrang-ing auxiliary hierarchical blocks and the corresponding blocks of automated formation of input actions for combinational cells are considered. A numerical assessment of the characteristics of each of the considered options is performed. A comparative analysis of the application of the proposed test structure for verifying libraries of standard digital elements in silicon is carried out. The proposed architecture was successfully applied in a test crystal for verification of three libraries of standard elements developed using the basic technology of JSC MERI CMOS 90 nm. The completeness of verification of the proposed test structure compared to the use of circuits from the ISCAS’85/89 sets is 6.19-6.31 times greater and reaches 99.94%. The area of the proposed structure is 2.29-4.65 times smaller.

A Radiation-Hardened Low-Power SRAM with Enhanced Write Capability for Space Applications

2025-06-20

Sang-Jin Kim , Sung-Hun Jo | Applied Sciences

With continued scaling of CMOS technology, the critical charge required for state retention in SRAM cells has decreased, leading to increased vulnerability to radiation-induced soft errors such as single-event upsets … With continued scaling of CMOS technology, the critical charge required for state retention in SRAM cells has decreased, leading to increased vulnerability to radiation-induced soft errors such as single-event upsets (SEUs) and single-event multi-node upsets (SEMNUs) in space environments. To address these reliability challenges, this paper proposes a 16-transistor radiation-hardened SRAM cell, EWS-16T, designed to improve resilience against soft errors. The performance of the proposed EWS-16T cell was evaluated through the 90 nm CMOS process and compared with previously reported radiation-hardened cells, including QCCS, SCCS, SAW16T, HP16T, RHSCC16T, and S8P8N. The results show that EWS-16T achieves the shortest write access time (22.11 ps) and the highest word line write trip voltage (WWTV) (279 mV) among all comparison cells. In addition, it demonstrates excellent performance in terms of critical charge tolerance (>300 fC) and low hold power consumption (53 nW). Furthermore, a comprehensive performance evaluation using the electrical quality metric (EQM) confirms that the EWS-16T cell achieves an outstanding balance among write efficiency, power consumption, and soft error resilience. These results indicate that EWS-16T is a highly promising SRAM design capable of ensuring reliable operation even in radiation-intensive space environments.

High-performance, low-area-overhead, and low-delay triple-node-upset self-recoverable latch design based on stacked transistors

2025-06-20

Hui Xu , Yue Dai , Ruijun Ma +6 more | Microelectronics Reliability

Single event upset cross section and total ionizing dose in simple commercial-off-the-shelf microelectronic devices using advanced proton, X-ray, and gamma radiation sources

2025-06-20

Željko Pastuović , Ryan Drury , Stefania Peracchi +5 more | The European Physical Journal Plus

Recent advances in network dismantling: A comprehensive review and list of recommendations for future work

2025-06-19

Sebastian Wandelt , Xinyue Chen , Xiaoqian Sun | Chaos Solitons & Fractals

Design of an energy-efficient soft error resilient RHBD SRAM cell with high read stability and minimum write errors

2025-06-19

Biby Joseph , R. K. Kavitha | Microelectronics Reliability

Fatores de risco para desenvolvimento de síndromes neurotóxicas por uso de células CAR-T: Uma revisão integrativa

2025-06-18

Leandro Maia Leão , Josemir de Almeida Lima , Uirassú Tupinambá Silva de Lima +5 more | Research Society and Development

A imunoterapia CAR-T é um tratamento inovador e de complexa tecnologia, que vem demonstrando eficácia em cânceres do sistema hematopoiético, porém, podem ocorrer efeitos adversos, tais como as síndromes neurotóxicas. … A imunoterapia CAR-T é um tratamento inovador e de complexa tecnologia, que vem demonstrando eficácia em cânceres do sistema hematopoiético, porém, podem ocorrer efeitos adversos, tais como as síndromes neurotóxicas. Objetivou-se analisar os fatores de risco associados ao desenvolvimento de síndromes neurotóxicas após infusão da imunoterapia CAR-T. Trata-se de uma revisão integrativa de abordagem qualitativa com caráter exploratório. A pesquisa ocorreu na base de dados PubMed, no período de tempo entre 2020 a 2025, utilizando a estratégia de busca: ‘’CAR-T Cell* Therapy’’ OR ‘’Immunotherapy AND CAR-T Cell*’’ AND ‘’Neurotoxicity Syndrome*’’ OR ‘’Cell-Associated Neurotoxicity’’; foram utilizados critérios do PRISMA2020, após aplicados critérios de inclusão e exclusão, os estudos selecionados foram analisados qualitativamente segundo os passos da Análise Textual Discursiva. Aplicados os critérios de inclusão e exclusão, 13 artigos foram selecionados para compor o estudo. Os fatores associados a maiores riscos de CRS e ICANS por imunoterapia CAR-T identificados são: tipos de produtos CAR, interleucinas inflamatórias liberadas simultaneamente, elevada carga tumoral, lesão renal aguda, sepse, histórico de lesão neurológica, início abrupto dos sintomas neurotóxicos e taxas elevadas de desidrogenase lática. Infere-se que diversos fatores influenciam nos riscos das neurotoxicidades, contribuindo na complexidade desse efeito, tornando-se necessária a realização de estudos adicionais para aprofundar a compreensão dos mecanismos envolvidos, identificar outros possíveis fatores de risco e viabilizar a padronização de protocolos farmacológicos de manejo para pacientes acometidos.

Enhancing Radiation Resilience and Throughput in Spaceborne RS(255,223) Encoder via Interleaved Pipelined Architecture

2025-06-16

Xiaodong Li , L. P. Zhou , Yan Zhu | Electronics

The error correction capability of the RS(255,223) code has been significantly enhanced compared to that of the RS(256,252) code, making it the preferred choice for the next generation of onboard … The error correction capability of the RS(255,223) code has been significantly enhanced compared to that of the RS(256,252) code, making it the preferred choice for the next generation of onboard solid-state recorders (O-SSRs). With the application of non-volatile double data rate (NV-DDR) interface technology in O-SSRs, instantaneous transmission rates of up to 1 Gbps per data I/O interface can be achieved. This development imposes higher requirements on the encoding throughput of RS encoders. For RS(255,223) encoders, throughput improvement is limited by the structures of serial architectures. The algorithm’s inherent characteristics restrict the depth of pipelining. In contrast, parallel solutions face bottlenecks in resource efficiency. To address these challenges, an interleaved pipelined architecture is proposed. By integrating interleaving technology within the pipeline, the structure overcomes the limitations of serial architectures. Using this architecture, a 36-stage pipelined RS(255,223) encoder is implemented. The throughput is greatly enhanced, and the radiation tolerance is also improved due to the application of interleaving techniques. The RS(255,223) encoder performance was evaluated on the Xilinx XC7K325T platform. The results confirm that the proposed architecture can support high data rates and provide effective error correction. With an 8-bit symbol size, a single encoder achieved throughput of 3.043 Gbps, making it highly suitable for deployment in future space exploration missions.

Exploration of alternative gate dielectric materials for RADFET sensors

2025-06-16

E. Amat , Carme Martínez‐Domingo , C. Fleta +2 more | Nuclear Instruments and Methods in Physics Research Section B Beam Interactions with Materials and Atoms

Analysis and Modeling of Single Event Transient Generation in Standard Combinational Cells

2025-06-12

Marko Andjelković , Miloš Krstić | Journal of Electronic Testing

EVs search for the 5-min charge

2025-06-12

special to C EN Sam Lemonick | C&EN Global Enterprise

Select an equation to calculate the dead time for a radiation counter system

2025-06-11

Quyet Dang Pham | International Journal of Science and Research Archive

Dead time is one of three critical parameters in the radiation measurement system that employs a GM counter tube. Dead time is determined using both accurate and approximation approaches. However, … Dead time is one of three critical parameters in the radiation measurement system that employs a GM counter tube. Dead time is determined using both accurate and approximation approaches. However, calculating the uncertainty of dead time using the exact method is challenging when instructing students. In this work, we present a method for selecting an equation from the approximation method to compute the dead time and its uncertainty, ensuring deviations are less than 5% when compared to the exact solution method.

Study on Atmospheric Neutron Single Event Effect of 650 V Silicon Carbide Diode

2025-06-01

Hong Zhang , Teng Ma | Journal of Physics Conference Series

Abstract Based on the Atmospheric Neutron Irradiation Spectrometer, the atmospheric neutron single event effect under five bias voltages for silicon carbide diodes with a rated voltage of 650 V was … Abstract Based on the Atmospheric Neutron Irradiation Spectrometer, the atmospheric neutron single event effect under five bias voltages for silicon carbide diodes with a rated voltage of 650 V was studied. As the bias voltage decreases, the single event burnout cross section of silicon carbide diodes gradually decreases. The electrical testing results show that the turn-on characteristics of silicon carbide diodes with single event burnout degrade and the breakdown characteristics are completely lost. The results of damage localization and characterization show that there are obvious cavity on the surface of silicon carbide diodes induced by single event burnout, and the current leakage path formed at the cavity is the main reason for the degradation of the electrical characteristics.

Characterization of sealed (zero gas flow) RPCs under strong irradiation

2025-06-01

A. Blanco , Marcio CARVALHO , S.T.G. Fetal +4 more | Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment

Investigation of heavy-ion induced degradation and catastrophic burnout mechanism in SiC diode

2025-06-01

Hong Zhang , Chao Peng , Teng Ma +4 more | Solid-State Electronics

Testing and fault tolerance techniques for carbon nanotube-based FPGAs

2025-06-01

Siyuan Lu , Kangwei Xu , Peng Xie +2 more | Integration

Enhancing radiation hardness and granularity in HV-CMOS: The RD50-MPW4 sensor

2025-06-01

B. Pilsl , T. Bergauer , Raimon Casanova +7 more | Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment

First study of single-event burnout in very-thin planar silicon sensors

2025-05-30

M. Ferrero , R. Arcidiacono , N. Cartiglia +7 more | Frontiers in Physics

This paper investigates the single-event burnout (SEB) effect in thin irradiated positive-intrinsic-negative (PiN) diodes and low-gain avalanche diodes (LGAD). SEB is a destructive event triggered in silicon sensors by the … This paper investigates the single-event burnout (SEB) effect in thin irradiated positive-intrinsic-negative (PiN) diodes and low-gain avalanche diodes (LGAD). SEB is a destructive event triggered in silicon sensors by the passage of a high-momentum charged particle. This effect arises in planar sensors under specific conditions: a significant ionization event caused by the particle’s passage and a very high electric field in the entire bulk region. The investigation of SEB was performed in two beam test campaigns: one at Deutsches Elektronen-Synchrotron (DESY) with an electron beam of <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="m1"><mml:mrow><mml:mn>3.6</mml:mn><mml:mtext> </mml:mtext><mml:mi mathvariant="normal">G</mml:mi><mml:mi mathvariant="normal">e</mml:mi><mml:mi mathvariant="normal">V</mml:mi><mml:mo>/</mml:mo><mml:mi mathvariant="normal">c</mml:mi></mml:mrow></mml:math> momentum and the second at CERN with a pion and proton beam of <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="m2"><mml:mrow><mml:mn>120</mml:mn><mml:mtext> </mml:mtext><mml:mi mathvariant="normal">G</mml:mi><mml:mi mathvariant="normal">e</mml:mi><mml:mi mathvariant="normal">V</mml:mi><mml:mo>/</mml:mo><mml:mi mathvariant="normal">c</mml:mi></mml:mrow></mml:math> momentum. The sensors under test had active thicknesses from <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="m3"><mml:mrow><mml:mn>15</mml:mn><mml:mtext> </mml:mtext><mml:mi>μ</mml:mi><mml:mi mathvariant="normal">m</mml:mi></mml:mrow></mml:math> to <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="m4"><mml:mrow><mml:mn>55</mml:mn><mml:mtext> </mml:mtext><mml:mi>μ</mml:mi><mml:mi mathvariant="normal">m</mml:mi></mml:mrow></mml:math> and active surfaces from <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="m5"><mml:mrow><mml:mn>1.7</mml:mn><mml:mtext> </mml:mtext><mml:mi mathvariant="normal">m</mml:mi><mml:msup><mml:mrow><mml:mi mathvariant="normal">m</mml:mi></mml:mrow><mml:mrow><mml:mn>2</mml:mn></mml:mrow></mml:msup></mml:mrow></mml:math> to <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="m6"><mml:mrow><mml:mn>433</mml:mn><mml:mtext> </mml:mtext><mml:mi mathvariant="normal">m</mml:mi><mml:msup><mml:mrow><mml:mi mathvariant="normal">m</mml:mi></mml:mrow><mml:mrow><mml:mn>2</mml:mn></mml:mrow></mml:msup></mml:mrow></mml:math> . In preparation for this study, most sensors were irradiated with neutrons up to a fluence of 1 <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="m7"><mml:mrow><mml:mo>⋅</mml:mo><mml:mn>1</mml:mn><mml:msup><mml:mrow><mml:mn>0</mml:mn></mml:mrow><mml:mrow><mml:mn>16</mml:mn></mml:mrow></mml:msup><mml:mtext> </mml:mtext><mml:msub><mml:mrow><mml:mi mathvariant="normal">n</mml:mi></mml:mrow><mml:mrow><mml:mi mathvariant="normal">e</mml:mi><mml:mi mathvariant="normal">q</mml:mi></mml:mrow></mml:msub><mml:mo>/</mml:mo><mml:mi mathvariant="normal">c</mml:mi><mml:msup><mml:mrow><mml:mi mathvariant="normal">m</mml:mi></mml:mrow><mml:mrow><mml:mn>2</mml:mn></mml:mrow></mml:msup></mml:mrow></mml:math> . The experimental setup for the beam tests included a frame for the alignment of the sensor with six available slots, two of which were equipped with trigger boards to monitor the beam rate during the test campaigns. This frame was placed inside a cold box to operate the irradiated sensors at very high electric fields while keeping their leakage current low. The experimental results show an inversely proportional relationship between the electric field at the SEB (SEB field) and the active thickness of the sensors. In this study, the SEB field increases from 11-12 V/ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="m8"><mml:mrow><mml:mi>μ</mml:mi></mml:mrow></mml:math> m in a 55- <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="m9"><mml:mrow><mml:mi>μ</mml:mi></mml:mrow></mml:math> m-thick sensor to 14 V/ <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="m10"><mml:mrow><mml:mi>μ</mml:mi></mml:mrow></mml:math> m in a 15–20 <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="m11"><mml:mrow><mml:mi>μ</mml:mi></mml:mrow></mml:math> m-thick sensor.

Design and Modeling of a New File Transfer Architecture to Reduce Undetected Errors Evaluated in the FABRIC Testbed

2025-05-27

Prateek Jain , Arash Sarabi , Ibrahim Matta +1 more | Proceedings of the ACM on Measurement and Analysis of Computing Systems

Ensuring the integrity of petabyte-scale file transfers is essential for the data gathered from scientific instruments. As packet sizes increase, so does the likelihood of errors, resulting in a higher … Ensuring the integrity of petabyte-scale file transfers is essential for the data gathered from scientific instruments. As packet sizes increase, so does the likelihood of errors, resulting in a higher probability of undetected errors in the packet. This paper presents a Multi-Level Error Detectio n (MLED) framework that leverages in-network resources to reduce undetected error probability (UEP) in file transmission. MLED is based on a configurable recursive architecture that organizes communication in layers at different levels, decoupling network functions such as error detection, routing, addressing, and security. Each layer L ij at level i implements a policy P ij that governs its operation, including the error detection mechanism used, specific to the scope of that layer. MLED can be configured to mimic the error detection mechanisms of existing large-scale file transfer protocols. The recursive structure of MLED is analyzed and it shows that adding additional levels of error detection reduces the overall UEP. An adversarial error model is designed to introduce errors into files that evade detection by multiple error detection policies. Through experimentation using the FABRIC testbed the traditional approach, with transport- and data link- layer error detection, results in a corrupt file transfer requiring retransmission of the entire file. Using its recursive structure, an implementation of MLED detects and corrects these adversarial errors at intermediate levels inside the network, avoiding file retransmission under non-zero error rates. MLED therefore achieves a 100% gain in goodput over the traditional approach, reaching a goodput of over 800 Mbps on a single connection with no appreciable increase in delay.

Analyzing the Effectiveness of Various NMOS Layouts for Total Ionizing Dose Hardening in 180nm CMOS

2025-05-27

Munish Malik , Neelam Rup Prakash , Ajay Kumar +3 more

Analysis of the SEU Tolerance of an FPGA-Based Time-to-Digital Converter Using Emulation-Based Fault Injection

2025-05-27

Roza Teklehaimanot Siecha , Getachew Alemu , Jeffrey Prinzie +1 more

In application domains where severe environmental conditions are unavoidable, including high-energy physics and nuclear power plants, accurate and dependable time-to-digital converters (TDCs) are essential components. Single-event upsets (SEUs) associated with … In application domains where severe environmental conditions are unavoidable, including high-energy physics and nuclear power plants, accurate and dependable time-to-digital converters (TDCs) are essential components. Single-event upsets (SEUs) associated with the configuration memory of field-programmable gate array (FPGA)-based implementations are becoming common sources of performance degradation even in terrestrial areas. Hence, the need to test and mitigate the effects of SEUs on FPGA-based TDCs is crucial to ensure that the design achieves reliable performance under critical conditions. The TMR SEM IP provides real-time fault injection, and dynamic SEU monitoring and correction in safety critical conditions without intervening with the functionality of the system, unlike traditional fault injection methods. This paper presents a scalable and fast fault emulation framework that tests the effects of SEUs on the configuration memory of a 5.7 ps-resolution TDC implemented on ZedBoard. The experimental results demonstrate that the standard deviation in mean bin width is 2.4964 ps for the golden TDC, but a 0.8% degradation in the deviation is observed when 3 million SEUs are injected, which corresponds to a 0.02 ps increment. Moreover, as the number of SEUs increases, the degradation in the RMS integral non-linearity (INL) of the TDC also increases, which shows 0.04 LSB (6.8%) and 0.05 LSB (8.8%) increments for 1 million and 3 million SEUs injected, respectively. The RMS differential non-linearity (DNL) of the faulty TDC with 3 million SEUs injected shows a 0.035 LSB (0.8%) increase compared to the golden TDC.

Radiation-Hardened 14T SRAM Cell Design for Double Node Upset Immunity in Space Applications

2025-05-26

Deep sub-micron memory technologies are essential parts of space-based electronics because of their vulnerability to Both double-end upsets (DNUs) and single-event upsets (SEUs). High-energy charged particles propagating through space can … Deep sub-micron memory technologies are essential parts of space-based electronics because of their vulnerability to Both double-end upsets (DNUs) and single-event upsets (SEUs). High-energy charged particles propagating through space can temporarily affect memory elements by disrupting the charge accumulated at critical nodes. A sturdy radiation-hardened-design (RHBD) SEI-14T SRAM cell, created especially for satellite and space systems, is presented in this work. The SEI-14T's dual-junction circuit layout lowers SEUs and DNUs across all sensing nodes with a self-correcting, state-reset feedback mechanism. Additionally, by maximizing the spatial spacing of the sensing zones, the design improves recovery from residual upset pairs. The performance advantages of the SEI-14T are illustrated by comparison with various state-of-the-art radiation-hardened memory cells, including the Quatro-10T, RHM-12T, RHD-12T, RSP-14T, RHPD-12T, RH-14T, EDP-12T, and QCCS-12T. The SEI-14T stands out with its remarkable read and write stability. At a supply voltage of 0.8V, the SEI-14T outperforms current designs by reducing steady-state power consumption by 20.82%, read access time by 23%, and write access time by 12.28%. In addition, the critical charge of the SEI-14T is significantly higher than that of alternative memory cells, with values that are 8.85, 6.56, 3.4, 5.75, 2.54, 2.47, 1.81, 1.63, and 1.44 times higher than those of 6T-SRAM, Quatro-10T, RHM-12T, RHD-12T, RSP-14T, RHPD-12T, RH-14T, EDP-12T, and QCCS-12T, respectively.

TID characterization of a serial transmitter core for high-energy physics experiments

2025-05-25

Xiaoting Li , Q. M. Zhu , Jiao-long Chen +7 more

Rapid prototyping of control modules for the DTT Plasma Control System

2025-05-22

Sara Dubbioso , Daniele Ottaviano , F. Fiorenza +5 more

Cyber defense in OCPP for EV charging security risks

2025-05-21

Safa Hamdare , David Brown , Devki Nandan Jha +6 more

RHLP-18T: A Radiation-Hardened 18T SRAM with Enhanced Read Stability and Low Power Consumption

2025-05-20

H Kim , Sung-Hun Jo

Electronic equipment in space is constantly exposed to high-energy particles, which can induce Single Event Upsets (SEUs) in memory components, threatening system reliability. To address this critical challenge, we propose … Electronic equipment in space is constantly exposed to high-energy particles, which can induce Single Event Upsets (SEUs) in memory components, threatening system reliability. To address this critical challenge, we propose RHLP-18T, a radiation-hardened 18-transistor (18T) Static Random-Access Memory (SRAM) cell designed to enhance robustness against radiation-induced faults. The proposed cell integrates circuit-level Radiation-Hardened-by-Design (RHBD) techniques to mitigate both SEUs and multi-node upsets. Comprehensive simulations were conducted using 90 nm CMOS technology, benchmarking RHLP-18T against nine existing RHBD cells (RHBD14T, HPHS12T, NRHC14T, QCCS12T, RHMC12T, RHWC12T, SEA14T, SIMR-18T, and SERSC16T). Simulation results demonstrate that the proposed RHLP-18T cell exhibits superior SEU tolerance, achieving a Read Static Noise Margin (RSNM) over three times higher than the next best design. Moreover, the proposed cell achieves the lowest hold power consumption among all evaluated cells. These improvements result in the highest Figure of Merit (FOM), indicating that RHLP-18T provides an optimal trade-off between robustness and overall performance for operation in radiation-exposed environments.

Design of GAMA-SHP microreactor for outer space application: Neutronic study

2025-05-20

Andang Widi Harto , Kusnanto Kusnanto , Alexander Agung +2 more