Engineering › Electrical and Electronic Engineering

Advancements in Semiconductor Devices and Circuit Design

Works Count: 88227

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Description

This cluster of papers explores the advancements in nanoelectronics, focusing on topics such as tunnel field-effect transistors, nanowire transistors, CMOS scaling limits, double-gate transistors, strained-silicon technology, quantum transport modeling, junctionless transistors, subthreshold swing, high-performance nanoscale devices, and process variation.

Keywords

Tunnel Field-Effect Transistors; Nanowire Transistors; CMOS Scaling; Double-Gate Transistors; Strained-Silicon Technology; Quantum Transport Modeling; Junctionless Transistors; Subthreshold Swing; High-Performance Nanoscale Devices; Process Variation

The Physics of Semi-Conductor Devices

1979-06-01

A. Quaranta

FinFETs and Other Multi-Gate Transistors

2007-10-16

Jean-Pierre Colinge

Physics of semiconductors

1995-06-01

John L. Moll

Transport in Nanostructures

2008-01-01

Stephen M. Goodnick

Fundamentals of Modern VLSI Devices

2009-08-06

Yuan Taur , T.H. Ning

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted … Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally renowned authors highlight the intricate interdependencies and subtle trade-offs between various practically important device parameters, and provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model and SiGe-base bipolar devices.

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A new method for determining the FET small-signal equivalent circuit

1988-07-01

G. Dambrine , A. Cappy , Frédéric Héliodore +1 more

A method to determine the small-signal equivalent circuit of FETs is proposed. This method consists of a direct determination of both the extrinsic and intrinsic small-signal parameters in a low-frequency … A method to determine the small-signal equivalent circuit of FETs is proposed. This method consists of a direct determination of both the extrinsic and intrinsic small-signal parameters in a low-frequency band. This method is fast and accurate, and the determined equivalent circuit fits the S-parameters well up to 26.5 GHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>

Low-Frequency Conductivity Due to Hopping Processes in Silicon

1961-06-15

M. Pollak , T. H. Geballe

The complex conductivity has been measured in $n$-type silicon with various kinds of impurities at frequencies between ${10}^{2}$ and ${10}^{5}$ cps and temperatures between 1 and 20\ifmmode^\circ\else\textdegree\fi{}K. In most cases … The complex conductivity has been measured in $n$-type silicon with various kinds of impurities at frequencies between ${10}^{2}$ and ${10}^{5}$ cps and temperatures between 1 and 20\ifmmode^\circ\else\textdegree\fi{}K. In most cases it is orders of magnitude larger than the measured dc conductivity and is attributed to polarization caused by hopping processes. The observed frequency dependence in the measured range can be expressed as $A{\ensuremath{\omega}}^{0.8}$, where $A$ is a complex constant. At the low-temperature end the conductivity is roughly proportional to minority impurity concentration and is almost independent of the majority impurity concentration and At higher temperatures the conductivity becomes approximately proportional to the product of both concentrations. A simple theory, based on the currently accepted model of impurity conduction, is given for the higher temperature range. It accounts well for the observed frequency and concentration dependences. However, only order-of-magnitude absolute agreement is obtained.

Logic Gates and Computation from Assembled Nanowire Building Blocks

2001-11-09

Yu Huang , Xiangfeng Duan , Yi Cui +3 more

Miniaturization in electronics through improvements in established "top-down" fabrication techniques is approaching the point where fundamental issues are expected to limit the dramatic increases in computing seen over the past … Miniaturization in electronics through improvements in established "top-down" fabrication techniques is approaching the point where fundamental issues are expected to limit the dramatic increases in computing seen over the past several decades. Here we report a "bottom-up" approach in which functional device elements and element arrays have been assembled from solution through the use of electronically well-defined semiconductor nanowire building blocks. We show that crossed nanowire p-n junctions and junction arrays can be assembled in over 95% yield with controllable electrical characteristics, and in addition, that these junctions can be used to create integrated nanoscale field-effect transistor arrays with nanowires as both the conducting channel and gate electrode. Nanowire junction arrays have been configured as key OR, AND, and NOR logic-gate structures with substantial gain and have been used to implement basic computation.

Physics and technology of semiconductor devices

1967-01-01

Andrew S. Grove

The Planar Technology. Solid-State Technology. Vapor-Phase Growth. Thermal Oxidation. Solid-State Diffusion. Semiconductors and Semiconductor Devices. Elements of Semiconductor Physics. Semiconductors under Non-Equilibrium Conditions. p-n Junction. Junction Transistor. Junction Field-Effect Transistors. … The Planar Technology. Solid-State Technology. Vapor-Phase Growth. Thermal Oxidation. Solid-State Diffusion. Semiconductors and Semiconductor Devices. Elements of Semiconductor Physics. Semiconductors under Non-Equilibrium Conditions. p-n Junction. Junction Transistor. Junction Field-Effect Transistors. Surface Effects and Surface-Controlled Devices. Theory of Semiconductor Surfaces. Surface Effects on p-n Junctions. Surface Field-Effect Transistors. Properties of the Silicon-Silicon Dioxide System.

Semiconductor Surface Physics

1957-12-31

Robert H. Kingston

Organic thin-film transistors: A review of recent advances

2001-01-01

Christos Dimitrakopoulos , Debra Mascaro

In this paper we review recent progress in materials, fabrication processes, device designs, and applications related to organic thin-film transistors (OTFTs), with an emphasis on papers published during the last … In this paper we review recent progress in materials, fabrication processes, device designs, and applications related to organic thin-film transistors (OTFTs), with an emphasis on papers published during the last three years. Some earlier papers that played an important role in shaping the OTFT field are included, and a number of previously published review papers that cover that early period more completely are referenced. We also review in more detail related work that originated at IBM during the last four years and has led to the fabrication of high-performance organic transistors on flexible, transparent plastic substrates requiring low operating voltages.

Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors

2004-12-09

Minjoo Larry Lee , Eugene A. Fitzgerald , Mayank T. Bulsara +2 more

This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones … This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the literature on short-channel device performance and process integration of strained Si. The review concludes with a global summary of the mobility enhancements available in the SiGe materials system and a discussion of implications for future technology generations.

Organic Transistors: Two-Dimensional Transport and Improved Electrical Characteristics

1995-04-14

A. Dodabalapur , Luisa Torsi , Howard E. Katz

The thiophene oligomer alpha-hexathienylene (alpha-6T) has been successfully used as the active semiconducting material in thin-film transistors. Field-induced conductivity in thin-film transistors with alpha-6T active layers occurs only near the … The thiophene oligomer alpha-hexathienylene (alpha-6T) has been successfully used as the active semiconducting material in thin-film transistors. Field-induced conductivity in thin-film transistors with alpha-6T active layers occurs only near the interfacial plane, whereas the residual conductivity caused by unintentional doping scales with the thickness of the layer. The two-dimensional nature of the field-induced conductivity is due not to any anisotropy in transport with respect to any molecular axis but to interface effects. Optimized methods of device fabrication have resulted in high field-effect mobilities and on/off current ratios of > 10(6). The current densities and switching speeds are good enough to allow consideration of these devices in practical large-area electronic circuits.

Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices

2007-12-06

Sayeef Salahuddin , Supriyo Datta

It is well-known that conventional field effect transistors (FETs) require a change in the channel potential of at least 60 mV at 300 K to effect a change in the … It is well-known that conventional field effect transistors (FETs) require a change in the channel potential of at least 60 mV at 300 K to effect a change in the current by a factor of 10, and this minimum subthreshold slope S puts a fundamental lower limit on the operating voltage and hence the power dissipation in standard FET-based switches. Here, we suggest that by replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation. The voltage transformer action can be understood intuitively as the result of an effective negative capacitance provided by the ferroelectric capacitor that arises from an internal positive feedback that in principle could be obtained from other microscopic mechanisms as well. Unlike other proposals to reduce S, this involves no change in the basic physics of the FET and thus does not affect its current drive or impose other restrictions.

Physics of Semiconductor Devices

1970-01-01

Geoffrey Pridham

Junctionless multigate field-effect transistor

2009-02-02

Chi‐Woo Lee , Aryan Afzalian , Nima Dehdashti Akhavan +3 more

This paper describes a metal-oxide-semiconductor (MOS) transistor concept in which there are no junctions. The channel doping is equal in concentration and type to the source and drain extension doping. … This paper describes a metal-oxide-semiconductor (MOS) transistor concept in which there are no junctions. The channel doping is equal in concentration and type to the source and drain extension doping. The proposed device is a thin and narrow multigate field-effect transistor, which can be fully depleted and turned off by the gate. Since this device has no junctions, it has simpler fabrication process, less variability, and better electrical properties than classical MOS devices with source and drain PN junctions.

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The physics of semiconductor devices

1979-12-01

H. L. Grubin

Transport and Deformation-Potential Theory for Many-Valley Semiconductors with Anisotropic Scattering

1956-02-01

Conyers Herring , Erich Vogt

A transport theory which allows for anisotropy in the scattering processes is developed for semiconductors with multiple nondegenerate band edge points. It is found that the main effects of scattering … A transport theory which allows for anisotropy in the scattering processes is developed for semiconductors with multiple nondegenerate band edge points. It is found that the main effects of scattering on the distribution function over each ellipsoidal constant-energy surface can be described by a set of three relaxation times, one for each principal direction; these are the principal components of an energy-dependent relaxation-time tensor. This approximate solution can be used if all scattering processes either conserve energy or randomize velocities. Expressions for mobility, Hall effect, low- and high-field magnetoresistance, piezoresistance, and high-frequency dielectric constant are derived in terms of the relaxation-time tensor. For static-field transport properties the effect of anisotropic scattering is merely to weight each component of the effective-mass tensor, as it appears in the usual theory, with the reciprocal of the corresponding component of the relaxation-time tensor.The deformation-potential method of Bardeen and Shockley is generalized to include scattering by transverse as well as longitudinal acoustic modes. This generalized theory is used to calculate the acoustic contributions to the components of the relaxation-time tensor in terms of the effective masses, elastic constants, and a set of deformation-potential constants. For $n$ silicon and $n$ germanium, one of the two deformation-potential constants can be obtained from piezoresistance data. The other one can at present only be roughly estimated, e.g., from the anisotropy of magnetoresistance. Insertion of these constants into the theory yields a value for the acoustic mobility of $n$ germanium which is in reasonable agreement with observation; a more accurate check of the theory may be possible when better input data are available. For $n$ silicon, available data do not suffice for a check of the theory.

An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications

1995-07-01

Christian Enz , Fran�ois Krummenacher , Eric A. Vittoz

Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

2007-08-01

Woo Young Choi , Byung‐Gook Park , Jong Duk Lee +1 more

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental … <para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the <emphasis emphasistype="smcaps">on</emphasis>/ <emphasis emphasistype="smcaps">off</emphasis> current ratio of the TFET was still lower than that of the MOSFET. In order to increase the <emphasis emphasistype="smcaps">on</emphasis> current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material. </para>

Nanowire transistors without junctions

2010-02-21

Jean-Pierre Colinge , Chi‐Woo Lee , Aryan Afzalian +7 more

1/f noise sources

1994-01-01

F.N. Hooge

This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with … This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>

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Design challenges of technology scaling

1999-01-01

Shekhar Borkar

Scaling advanced CMOS technology to the next generation improves performance, increases transistor density, and reduces power consumption. Technology scaling typically has three main goals: 1) reduce gate delay by 30%, … Scaling advanced CMOS technology to the next generation improves performance, increases transistor density, and reduces power consumption. Technology scaling typically has three main goals: 1) reduce gate delay by 30%, resulting in an increase in operating frequency of about 43%; 2) double transistor density; and 3) reduce energy per transition by about 65%, saving 50% of power (at a 43% increase in frequency). These are not ad hoc goals; rather, they follow scaling theory. This article looks closely at past trends in technology scaling and how well microprocessor technology and products have met these goals. It also projects the challenges that lie ahead if these trends continue. This analysis uses data from various Intel microprocessors; however, this study is equally applicable to other types of logic designs. Is process technology meeting the goals predicted by scaling theory? An analysis of microprocessor performance, transistor density, and power trends through successive technology generations helps identify potential limiters of scaling, performance, and integration.

Device scaling limits of Si MOSFETs and their application dependencies

2001-03-01

D.J. Frank , R.H. Dennard , E. Nowak +3 more

This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in … This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

Silicon quantum electronics

2013-07-10

Floris A. Zwanenburg , Andrew S. Dzurak , Andrea Morello +6 more

This review describes recent groundbreaking results in Si, $\mathrm{Si}/\mathrm{SiGe}$, and dopant-based quantum dots, and it highlights the remarkable advances in Si-based quantum physics that have occurred in the past few … This review describes recent groundbreaking results in Si, $\mathrm{Si}/\mathrm{SiGe}$, and dopant-based quantum dots, and it highlights the remarkable advances in Si-based quantum physics that have occurred in the past few years. This progress has been possible thanks to materials development of Si quantum devices, and the physical understanding of quantum effects in silicon. Recent critical steps include the isolation of single electrons, the observation of spin blockade, and single-shot readout of individual electron spins in both dopants and gated quantum dots in Si. Each of these results has come with physics that was not anticipated from previous work in other material systems. These advances underline the significant progress toward the realization of spin quantum bits in a material with a long spin coherence time, crucial for quantum computation and spintronics.

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Spin-Orbit Interaction and Magnetoresistance in the Two Dimensional Random System

1980-02-01

S. Hikami , A. I. Larkin , Yasutaka Nagaoka

Effect of the spin-orbit interaction is studied for the random potential scattering in two dimensions by the renormalization group method. It is shown that the localization behaviors are classified in … Effect of the spin-orbit interaction is studied for the random potential scattering in two dimensions by the renormalization group method. It is shown that the localization behaviors are classified in the three different types depending on the symmetry. The recent observation of the negative magnetoresistance of MOSFET is discussed.

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Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas

1990-04-01

T. Sakurai , A. Richard Newton

An alpha -power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced. The model is an extension of Shockley's square-law MOS model … An alpha -power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced. The model is an extension of Shockley's square-law MOS model in the saturation region. Since the model is simple, it can be used to handle MOSFET circuits analytically and can predict the circuit behavior in the submicrometer region. Using the model, closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived. The delay expression includes input waveform slope effects and parasitic drain/source resistance effects and can be used in simulation and/or optimization CAD tools. It is found that the CMOS inverter delay becomes less sensitive to the input waveform slope and that short-circuit dissipation increases as the carrier velocity saturation effect in short-channel MOSFETs gets more severe.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>

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FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

2000-01-01

Chenming Hu , Jeffrey Bokor , Tsu‐Jae King +7 more

MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed. By using boron-doped Si/sub 0.4/Ge/sub 0.6/ … MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed. By using boron-doped Si/sub 0.4/Ge/sub 0.6/ as a gate material, the desired threshold voltage was achieved for the ultrathin body device. The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily using the conventional planar MOSFET process technologies.

Multiple-gate SOI MOSFETs

2004-01-27

Jean-Pierre Colinge

On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration

1994-01-01

S. Takagi , Akira Toriumi , M. Iwase +1 more

This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup … This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>

Matching properties of MOS transistors

1989-10-01

Marcel Pelgrom , Aad C.J. Duinmaijer , A.P.G. Welbers

The matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as … The matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for long-distance matching and rotation of devices. Matching parameters of several processes are compared. The matching results have been verified by measurements and calculations on several basic circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>

Heterostructure bipolar transistors and integrated circuits

1982-01-01

H. Kroemer

Two new epitaxial technologies have emerged in recent years (molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD)), which offer the promise of making highly advanced heterostructures routinely available. … Two new epitaxial technologies have emerged in recent years (molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD)), which offer the promise of making highly advanced heterostructures routinely available. While many kinds of devices will benefit, the principal and first beneficiary will be bipolar transistors. The underlying central principle is the use of energy gap variations beside electric fields to control the forces acting on electrons and holes, separately and independently of each other. The resulting greater design freedom permits a re-optimization of doping levels and geometries, leading to higher speed devices. Microwave transistors with maximum oscillation frequencies above 100 GHz and digital switching transistors with switching times below 10 ps should become available. An inverted transistor strucure with a smaller collectors on top and a larger emitter on the bottom becomes possible, with speed advantages over the common "emitter-up" design. Double-heterostructure (DH) transistors with both wide-gap emitters and collectors offer additional advantages. They exhibit better performance under saturated operation. Their emitters and collectors may be interchanged by simply changing biasing conditions, greatly simplifying the architecture of bipolar IC's. Examples of heterostructure implementations of I 2 L and ECL are discussed. The present overwhelming dominance of the compound semiconductor device field by FET's is likely to come to an end, with bipolar devices assuming an at least equal role, and very likely a leading one.

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CMOS scaling into the nanometer regime

1997-04-01

Yuan Taur , D. A. Buchanan , Wei Chen +7 more

Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime … Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling.

Low-power CMOS digital design

1992-04-01

Anantha P. Chandrakasan , S. Sheng , R.W. Brodersen

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power … Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughput. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>

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A subthermionic tunnel field-effect transistor with an atomically thin channel

2015-09-29

Deblina Sarkar , Xuejun Xie , Wei Liu +6 more

The physics of semiconductor devices

1970-04-01

R. H. Rediker

Physics of Semiconductor Devices

2006-04-10

Simon M. Sze , Kwok K. Ng

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VLSI Electronics Microstructure Science

1985-01-01

Norman G. Einspruch

The Physics of Semiconductor Devices

2024-01-01

Physics of Semiconductor Devices

1966-01-01

J.R. ABRAHAMS , Geoffrey Pridham

Physics of Semiconductor Devices

2002-01-01

J.-P. Colinge , Cindy Colinge

Physics of semiconductor devices

1990-07-01

Device physics of heterostructure and quantum devices advanced discrete devices characterization of semiconducting materials, unit processes and devices futuristic devices. Device physics of heterostructure and quantum devices advanced discrete devices characterization of semiconducting materials, unit processes and devices futuristic devices.

Theory of Surface States

1965-06-14

Volker Heine

The properties of metal-to-semiconductor junctions and of free semiconductor surfaces are usually explained on the basis of surface states. The theory of the metal contacts is discussed critically, because strictly … The properties of metal-to-semiconductor junctions and of free semiconductor surfaces are usually explained on the basis of surface states. The theory of the metal contacts is discussed critically, because strictly speaking localized surface states cannot exist in such junctions. However, it is shown that virtual or resonance surface states can exist which behave for practical purposes in the same way. They are really the tails of the metal wave functions rather than separate states. In the past, the length of this tail has often been ignored. Some estimates of its length are made and its consequences pointed out. A semiquantitative discussion is given of various recent data, including the effect of an oxide layer on barrier height, the variation of barrier height with the metal, the work function of a free surface at high doping, and the effect of a cesium layer on the work function.

Analysis and Simulation of Semiconductor Devices

1984-01-01

S. Selberherr

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High field transport in semiconductors

1967-01-01

E. M. Conwell

Asymmetric Drain-Engineered Vertical Tunnel Field Effect Transistor: Design, Simulation, and Performance Optimization

2025-06-25

V. Saraswathi , N. Siddaiah | Transactions on Electrical and Electronic Materials

Performance of Gate Stack Silicon on Insulator and Gate Stack Pocket‐Doped Silicon on Insulator Tunnel FETs with Interface Trap Charges

2025-06-25

Rajesh Saha | physica status solidi (a)

In this article, the effect of interface trap charges (ITCs) on Gate Stack Silicon on Insulator (GSSOI) and GSSOI with counter‐doped pocket (GSCDPSOI) tunnel field effect transistors (TFETs) has been … In this article, the effect of interface trap charges (ITCs) on Gate Stack Silicon on Insulator (GSSOI) and GSSOI with counter‐doped pocket (GSCDPSOI) tunnel field effect transistors (TFETs) has been highlighted using Sentaurus TCAD simulator. Such analysis is reported for two different trap distributions like Gaussian and uniform trap distributions. The various parameters like electron density, transfer characteristics, electric field, energy band diagram, subthreshold swing, and current ratio are reported for these TFETs under the presence of Gaussian and uniform distribution of trap charges. Further, the RF/analog performance like transconductance ( g m ) and cut‐off frequency ( f T ) are extracted for these TFETs considering Gaussian and uniform distribution of trap charges. It is seen that the electrical parameters of GSCDPSOI TFET are more immune to ITCs compared to GSSOI TFET. Moreover, the presence of pocket in GSCDPSOI TFET leads to enhanced BTBT rate; thus, the performance of electrical behavior is improved.

A Hybrid Machine Learning Model to Predict Reconfigurable FET Characteristics with Limited Dataset

2025-06-25

Chithraja Rajan , Aditya R Babhulkar , Karishma Nakhathe +2 more | Semiconductor Science and Technology

Abstract Reconfigurable Field-Effect Transistors (RFETs) can dynamically switch between n-type and p-type conduction, making them ideal for power-efficient applications. However, modeling RFET behavior remains computationally intensive due to complex charge … Abstract Reconfigurable Field-Effect Transistors (RFETs) can dynamically switch between n-type and p-type conduction, making them ideal for power-efficient applications. However, modeling RFET behavior remains computationally intensive due to complex charge transport mechanisms. This work presents a machine learning (ML) approach to predict RFET characteristics using a minimal dataset, reducing computational costs while maintaining accuracy. Various ML models, including ANN, LSTM, Logistic Regression, and polynomial models, were tested, revealing limitations in capturing RFET behavior. To overcome this, we developed a hybrid model combining linear and polynomial techniques with a feedback mechanism to enhance accuracy. Trained on TCAD-simulated data for hetero-dielectric (HD) hetero-material (HM) RFETs across five mole fractions, the model accurately predicted electrical characteristics for unknown fractions. It achieved 98\% accuracy for n-type and 92\% for p-type devices. Our approach provides a resource-efficient alternative to traditional physics-based models, requiring just 100 rows and three columns of training data.

Multiobjective Design and Performance Evaluation of <scp>III–V</scp> High‐<scp>k</scp> Surrounding Gate Tunnel Field Effect Transistors Using Machine Learning Approaches

2025-06-24

V. Charumathi , N. B. Balamurugan , M. Suguna +1 more | International Journal of Numerical Modelling Electronic Networks Devices and Fields

ABSTRACT In this work, utilising the MultiObjective Optimisation (MOO) framework, III–V tunnel field effect transistors with surrounding gate (III–V TFETs [SG]) have been designed to optimise speed, power and variation … ABSTRACT In this work, utilising the MultiObjective Optimisation (MOO) framework, III–V tunnel field effect transistors with surrounding gate (III–V TFETs [SG]) have been designed to optimise speed, power and variation for improved device logic parameters. III–V TFET are enhanced by combining the advantages of high‐k Hafnium dioxide (HfO 2 ) dielectric and surrounding gate technologies. III–V TFETs (SG) have collaborated with indium arsenide (InAs) and gallium antimonide (GaSb) to offer better electron mobility, which further improves device performance. By augmenting the MOO framework and machine learning (ML) methods, we have performed the optimisation of III–V high‐k TFETs with surrounding gate (III–V high‐k TFETs [SG]) by efficiently handling the competing targets. Two advanced MOO algorithms—Non‐Dominated Sorting (NS) Genetic Algorithm‐III (GA‐III) and Pareto Active‐Learning Algorithm (PA‐L)—are examined. Moreover, it has been demonstrated that ML‐based MOO can automatically identify the best solutions for III–V high‐k TFETs with Surrounding Gate, influencing the development of the next generation of nanoscale transistors.

High-Power Semiconductor Devices

2025-06-24

Dorin O. Neacșu | CRC Press eBooks

Voltage noise thermometry in integrated circuits at millikelvin temperatures

2025-06-23

G. Ridgard , Michael D. Thompson , Lea Schreckenberg +5 more | Journal of Applied Physics

This paper demonstrates the use of voltage noise thermometry, with a cross-correlation technique, as a dissipation-free method of thermometry inside a CMOS integrated circuit (IC). We show that this technique … This paper demonstrates the use of voltage noise thermometry, with a cross-correlation technique, as a dissipation-free method of thermometry inside a CMOS integrated circuit (IC). We show that this technique exhibits broad agreement with the refrigerator temperature range from 300 mK to 8 K. Furthermore, it shows substantial agreement with both an independent in-IC thermometry technique and a simple thermal model as a function of power dissipation inside the IC. As the device under a test is a resistor, it is feasible to extend this technique by placing many resistors in an IC to monitor the local temperatures, without increasing IC design complexity. This could lead to better understanding of the thermal profile of ICs at cryogenic temperatures. This has its greatest potential application in quantum computing, where the temperature at the cold classical-quantum boundary must be carefully controlled to maintain qubit performance.

Quantum Kernel Learning for Small Dataset Modeling in Semiconductor Fabrication: Application to Ohmic Contact

2025-06-23

Zeheng Wang , Fangzhou Wang , Liang Li +5 more | Advanced Science

Modeling complex semiconductor fabrication processes such as Ohmic contact formation remains challenging due to high-dimensional parameter spaces and limited experimental data. While classical machine learning (CML) approaches have been successful … Modeling complex semiconductor fabrication processes such as Ohmic contact formation remains challenging due to high-dimensional parameter spaces and limited experimental data. While classical machine learning (CML) approaches have been successful in many domains, their performance degrades in small-sample, nonlinear scenarios. In this work, quantum machine learning (QML) is investigated as an alternative, exploiting quantum kernels to capture intricate correlations from compact datasets. Using only 159 experimental GaN HEMT samples, a quantum kernel-aligned regressor (QKAR) is developed combining a shallow Pauli-Z feature map with a trainable quantum kernel alignment (QKA) layer. All models, including seven baseline CML regressors, are evaluated under a unified PCA-based preprocessing pipeline to ensure a fair comparison. QKAR consistently outperforms classical baselines across multiple metrics (MAE, MSE, RMSE), achieving a mean absolute error of 0.338 Ω·mm when validated on experimental data. Noise robustness and generalization are further assessed through cross-validation and new device fabrication. These findings suggest that carefully constructed QML models can provide predictive advantages in data-constrained semiconductor modeling, offering a foundation for practical deployment on near-term quantum hardware. While challenges remain for both QML and CML, this study demonstrates QML's potential as a complementary approach in complex process modeling tasks.

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Optimization and Design of Silicon PIN Detector Guard Ring Structure

2025-06-20

Yu Chen | Applied and Computational Engineering

In this study, TCAD Silvaco software is utilized to simulate a silicon-based PIN guard ring detector, focusing on the role of the guard ring in electric field shaping and breakdown … In this study, TCAD Silvaco software is utilized to simulate a silicon-based PIN guard ring detector, focusing on the role of the guard ring in electric field shaping and breakdown suppression. The lateral and vertical structures of the device are optimized by constructing a multi-stage gradient guard ring system. The non-uniform meshing technique and Newton-Raphson iterative algorithm are used to accurately simulate the critical region and solve the coupling problem of the equations, and the I-V curves reveal the characteristics of the device under reverse and forward bias, and the guard ring can effectively reduce the concentration effect of the electric field and avoid the risk of edge breakdown. This paper shows that the guard ring structure improves the detector E-field breakdown resistance and optimizes the edge E-field shaping.

Work function engineered polarity-controlled TFET for digital circuit applications: design and performance analysis

2025-06-20

Sajai Vir Singh , Mukesh Kumar Bind , Kaushal Nigam +1 more | Analog Integrated Circuits and Signal Processing

Performance enhancement of triple material staggered heterojunction double gate MOSFET (TM-SH-DGMOS) with gate engineering

2025-06-20

Prasanta Ku Khuntia , Kishore Ch Singh , Biswajit Baral +1 more | Deleted Journal

Digital Control Active Gate Driver for WBG Power Semiconductors with Independent Control of Switching Losses and Overshoot

2025-06-19

Yixuan Kang , Kyung-Min Kim , Rae-Young Kim | The Transactions of the Korean Institute of Power Electronics

A Virtually Doped Hetero Z-Shaped Charge Plasma TFET Based Label Free Biosensor

2025-06-19

Ragini Singh , Vishalli Ghai , Alok Naugarhiya +1 more | Sensing and Imaging

High-Temperature Ultrasensitive FET-Based CVD Graphene Hall Probes

2025-06-18

Linda Supalová , Miroslav Bartošík , Vojtěch Švarc +5 more | ACS Applied Electronic Materials

Metal-Pair Engineered Cylindrical GAAFET with Asymmetric Doping for Enhanced Performance

2025-06-17

Jitendra Kumar , D. Satyanarayana | Transactions on Electrical and Electronic Materials

VQE-generated quantum circuit dataset for machine learning

2025-06-17

NULL AUTHOR_ID | Physical Review Research

Rapid optimal work extraction from a quantum-dot information engine

2025-06-16

NULL AUTHOR_ID | Physical Review Research

Analog and RF Performance Analysis of Double-Gate CNT-FETs with Asymmetric Source/Drain Extensions

2025-06-16

Md Akram Ahmad | Physica Scripta

Abstract This work presents a comprehensive analysis of the analog and radio-frequency (RF) performance of double-gate carbon nanotube field-effect transistors (DG CNT-FETs) employing asymmetric underlap (AUL) engineering. The investigation is … Abstract This work presents a comprehensive analysis of the analog and radio-frequency (RF) performance of double-gate carbon nanotube field-effect transistors (DG CNT-FETs) employing asymmetric underlap (AUL) engineering. The investigation is carried out using self-consistent atomistic simulations based on the non-equilibrium Green’s function (NEGF) formalism. Initially, the optimal AUL length is determined by evaluating the ON/OFF current ratio (ION/IOFF), a critical metric for digital performance. Subsequently, various analog and RF figures of merit (FoMs) are analyzed, including transconductance (gm), output resistance (r0), intrinsic gain (gmr0), cut-off frequency (fT), transconductance generation factor (TGF), gain frequency product (GFP), and gain transfer frequency product (GTFP). The results indicate that AUL engineering significantly enhances key performance parameters such as ION/IOFF, r0, gmr0, GFP, and GTFP. Specifically, an 8 nm AUL leads to a 970% increase in ION/IOFF, a 70.38% improvement in TGF, a 360% enhancement in intrinsic gain, and notable improvements in GFP (81.44%) and GTFP (150.5%) compared to conventional CNT-FETs. However, fT and TFP are reduced by 77.4% and 36.2%, respectively. These findings highlight critical trade-offs and offer valuable design insights for optimizing CNT-FETs in next-generation analog and RF circuits.

High-sensitivity near-infrared photosensor based on electron–hole bilayer TFET

2025-06-16

Hu Liu , Pengyu Wang , Mingze Du +3 more | The European Physical Journal Plus

A Novel Approach to Determine the Type of Conductivity in Semiconductors Using a Combined Seebeck and Peltier Effects

2025-06-14

Nora Faik Numan , Omar A. Abdulrazzaq , Sura Noori Atewi +2 more | Iraqi Journal of Industrial Research

This work presents a novel Seebeck system design that utilizes the Peltier effect to determine the conductivity type of semiconductors, a critical aspect of semiconductor research. The study investigates the … This work presents a novel Seebeck system design that utilizes the Peltier effect to determine the conductivity type of semiconductors, a critical aspect of semiconductor research. The study investigates the combined influence of the Seebeck and Peltier thermoelectric phenomena, which generate a voltage difference in response to temperature fluctuations and vice versa in semiconductors. The proposed system is an advancement over conventional Seebeck systems, which typically require significant power for heating and cooling. By incorporating a Peltier module as both a cooling and heating source, the system significantly reduces energy consumption and enables solar-powered operation. Laboratory experiments were conducted on silicon specimens under varying thermal conditions to validate the system's effectiveness. The results confirmed the system's ability to accurately determine semiconductor conductivity type by analyzing its response to temperature gradients. The findings demonstrated that a greater temperature difference between the hot and cold ends increases the generated electrical potential until thermal equilibrium is reached. This study presents the device’s efficiency, particularly its rapid response to temperature fluctuations and its capability for precise thermal regulation in practical applications. This innovative design represents a significant advancement in thermoelectric research, offering a more sustainable and energy-efficient alternative to traditional Seebeck and Hall Effect devices, thereby enhancing semiconductor conductivity analysis techniques.

The influence of contact interfaces on transport statistics in field-effect transistors based on highly-doped InAs nanowires

2025-06-14

А. Zhukov | Physica E Low-dimensional Systems and Nanostructures

Fourier Series-Based Analytical Model for Channel Potential of Dual Material Gate SOI Junctionless FinFET

2025-06-14

Shara Mathew , Rathnamala Rao | Journal of Electronic Materials

Performance Evaluation of Charge Plasma-Assisted Homo and Hetero Structure Based DG-JL-TFET for Low-Power Analog/RF Applications

2025-06-14

Tamilarasi Raja , Karthik Sekhar | Transactions on Electrical and Electronic Materials

Observation of 1/f4 Noise in Organic Bilayer Ambipolar FETs and Proposition of Defect Engineering Method for Ultimate Noise Control

2025-06-13

Young-Min Han , J. Q. Song , Ryun‐Han Koo +2 more | Advanced Electronic Materials

Abstract The omnipresence of low‐frequency noise (LFN) within semiconductor materials and devices poses a substantial concern for the reliability of integrated circuits (ICs). Consequently, considerable research endeavors are directed toward … Abstract The omnipresence of low‐frequency noise (LFN) within semiconductor materials and devices poses a substantial concern for the reliability of integrated circuits (ICs). Consequently, considerable research endeavors are directed toward characterizing LFN across various types of field‐effect transistors (FETs), pivotal components in IC. Here, the LFN characteristics of bilayer ambipolar FETs based on organic semiconductors are investigated, / uri / We report that interface defects at the n/p junctions engender a correlation between trapping/detrapping noise and generation/recombination noise, resulting in a 1/ f 4 noise. The elucidation of this distinctive noise behavior is conducted through comprehensive and comparative studies on LFN of single n‐ and p‐channel FETs. Furthermore, a novel approach is proposed to control excess noise in bilayer ambipolar FETs by inserting a thin insulator layer (parylene) between the n/p junction. This yields a notable reduction in noise amplitude, concurrently leading to the dissolution of 1/ f 4 noise into 1/ f 3 and 1/ f 2 components. This study not only furnishes the inaugural report of the underlying mechanism behind the unique 1/ f 4 noise but also presents a pragmatic strategy for its control, thereby opening a new horizon for LFN studies on organic‐based FETs.

Characterization and applications of direct current microarcs: a review

2025-06-13

Margarita Baeva , Dirk Uhrlandt | Journal of Physics D Applied Physics

Abstract An overview of the applications and the characterization of micro-sized direct current arcs is provided, with emphasis on their classification among other discharge kinds (glow discharges, sparks, gliding and … Abstract An overview of the applications and the characterization of micro-sized direct current arcs is provided, with emphasis on their classification among other discharge kinds (glow discharges, sparks, gliding and thermal arcs). Industrial applications such as Micro Plasma Arc Welding, Wire Arc Additive Manufacturing, and low-voltage switching are considered and typical operating conditions are given. Specific diagnostic studies, which are reported so far, are summarized to present electrical and spectroscopic measurements, and selected findings. The modelling of microarcs is described and the available approaches are explained. The equations for a self-consistent fluid modelling of microarcs and their electrodes are presented with the main focus on the unified description of the plasma region and the boundary conditions. This description provides the spatial structure and the plasma parameters, which can hardly be obtained in experiments. Simulation results for various gases and cathode types are presented in relation to applications included in the review.

Simulating Scaling Effects in Fully Vertical GaN FinFETs

2025-06-12

Alexander Simko , Navya Sri Garigapati , Adamantia Logotheti +2 more | physica status solidi (a)

Herein, it is shown that a fully vertical GaN FinFET can reach close to ideal Baliga's figure of merit (BFOM) for thicker drift layers. Devices with drift layers between 1 … Herein, it is shown that a fully vertical GaN FinFET can reach close to ideal Baliga's figure of merit (BFOM) for thicker drift layers. Devices with drift layers between 1 and 8 are simulated using TCAD, and the device geometry is varied to find optimal device performance. For 8 drift layers, device operation at the BFOM limit is found with and . An optimal switching FOM at is found.

An intuitionistic model for evaluating the dopant profiles in C-BAs MOSFETs: integrating capacitance–voltage method for large scale applications

2025-06-12

Harikrishnan Perumalsamy , P. Sivakumar , Suresh Muthusamy +1 more | Analog Integrated Circuits and Signal Processing

Understanding the Nanowire Material-Dependent Charge Qubit Performance of Voltage-Tunable Double Quantum Dot Gate Nanowire Channel Field-Effect Transistors (DQD-NWFETs)

2025-06-11

Nilayan Paul , Sanatan Chattopadhyay | Journal of Electronic Materials

An Optimized Design Method for Enhancing Efficiency of LLC Secondary Side MOSFETs Using Current‐Source Gate Driver

2025-06-11

Ziyan Zhou , Song Ding , Qi Liu +2 more | International Journal of Circuit Theory and Applications

ABSTRACT Various resonant gate driver circuits aim to recover gate drive losses and reduce switching losses, particularly in high‐frequency applications, enhancing overall system efficiency. The LLC resonant converter is favored … ABSTRACT Various resonant gate driver circuits aim to recover gate drive losses and reduce switching losses, particularly in high‐frequency applications, enhancing overall system efficiency. The LLC resonant converter is favored in high‐frequency, high‐power‐density settings due to its soft‐switching capabilities. However, existing gate driver circuits for LLC converters usually operate at fixed frequencies and duty cycles, failing to address the variable requirements of LLC voltage regulation. Most current variable frequency and duty cycle drivers focus on buck converters, targeting large current handling without optimization for LLC circuits. A dual‐channel current‐source gate driver for secondary‐side MOSFETs in LLC‐DCX is proposed in this paper. This circuit enables variable‐frequency and duty‐cycle control. Specifically for LLC‐DCX applications, an optimized design utilizing current‐source gate drivers to control the LLC secondary rectifier is presented. The loss mechanisms in current‐source drive circuits are analyzed, and a comprehensive loss model for the LLC circuit is established. Key resonant parameters of the driver are optimized along with the dead‐time adjustment of the LLC converter. A prototype LLC converter was developed, operating at a resonant frequency of 1.3 MHz. Testing results show that the LLC prototype driven by the current‐source gate driver achieves a peak efficiency improvement of 0.67% compared with traditional drivers and recovers 82% of gate drive energy.

The DOS Functions in MOSFETs under Accumulation and Inversion Modes of Operation of Non-Parabolic Materials and the Quantum Capacitance

2025-06-08

| Series on the foundations of natural science and technology

Low-cost fabrication of organic rectifying diodes for high-speed AC/DC conversion

2025-06-03

Norio Onojima , Ryousei Matsumoto , K. Hatano +1 more | Organic Electronics